This invention relates generally to analog-to-digital (A/D) converters. Specifically, the present invention relates to A/D converters which are suitable for high speed operation. More specifically, the present invention relates to A/D converters having an architecture which lends itself to expansion to achieve a greater precision digital output.
Prior art devices confront problems of converting an analog signal into a digital representation of the analog signal. One high speed approach is the "Flash" or parallel comparison type A/D converter. In a parallel comparison type A/D converter an input analog signal is compared with a multiplicity of reference voltages by a multiplicity of analog comparators. Digital outputs from the multiplicity of analog comparators are encoded into an acceptable digital output code. The parallel comparison A/D converter establishes the multiplicity of reference voltages through the use of a multiplicity of series connected resistors which are coupled between maximum reference voltages.
Such parallel comparison type A/D converters have several drawbacks. For example, each of the multiplicity of series connected resistors requires a relatively large area when these resistors are implemented in an integrated circuit. Furthermore, these resistors must exhibit extremely precise values and are typically laser trimmed. A relatively high cost device results.
Additionally, the parallel comparison type A/D converters do not readily expand to achieve a greater precision digital output. Each added bit of output precision increases circuit complexity by a factor of 2. Furthermore, the large number of comparators which the analog input signal feeds causes loading problems which are typically cured in a manner that slows overall conversion time.